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[AK8853XQ/ vn] rev-e-00 1 2008/01 AK8853XQ/ vn ntsc/pal/secam digital video decoder overview the ak8853 is a single-chip digital decoder for ntsc, pal, and secam composite video signals. its output data is in ycbcr format, compliant with itu- r bt.601. its pixel clock, with a generated clock rate of 27 mhz, synchronizes with the input signal. its output interface is itu-r bt.656 compliant. closed-caption, vbid, and wss enc oded information in the input signal is externally accessible. microprocessor access is via a i 2 c interface. features decodes composite video signals ntsc (j, m, 4.43), pal (b, d, g, h, i, m, n, nc, 60), secam. four input channels, with internal video switch. 10-bit adc 1 channel. internal line-locked and frame-locked plls for gener ation of clock synchronized with input signal. internal pga (-6 db to 6 db). adaptive automatic gai n control (agc). auto color control (acc). image adjustment (contrast, saturati on, brightness, hue, sharpness). automatic input signal detection. adaptive 2-d y/c separation. pal decoding phase correction. itu-r bt.656 format output (wit h 4:2:2_8 bit parallel_eav/sav) closed-caption signal decodi ng (output via register). wss signal decoding (output via register). macrovision signal detection (m acrovision certification). power down function. i 2 c control. 1.70~2.00 v core power supply. 1.70~3.60 v interface power supply. operating temperature range: ? 40c to 105c. (AK8853XQ) operating temperature range: ? 40c to 85c. (ak8853vn) 48-pin lqfp package. (AK8853XQ) 48-pin qfn package. (ak8853vn) (note) the difference between AK8853XQ and ak8853vn is operating temperature range and package type.
[AK8853XQ/ vn] rev-e-00 2 2008/01 1. functional block diagram test logic microprocessor interface yc separation decimation filter 10-bit adc pga aafilter clamp mux clock module timing controller digital pll sync separation luminance process chrominance process vbi decoding vref hd output buffer vd_f dvalid_f nsig dtclk data[7:0] avss avdd dvdd dvss pvdd1 pvdd2 vcom vrn iref atio vrp ain4 ain3 ain2 ain1 test0 test1 xti xto clkmd sela rstn oe pdn sda scl cvbs 27mhz cvbs y c
[AK8853XQ/ vn] rev-e-00 3 2008/01 2. pin assignment ? 48 pins lqfp/ 48 pins qfn 1 2 3 4 10 689 7 51112 20 13 18 17 16 15 14 19 24 22 21 23 27 26 25 30 29 28 33 32 31 36 35 34 41 48 43 44 45 46 47 42 37 39 40 38 a in4 vcom a tio a vss iref a vdd a vss xto dvss xti dvdd clkmd vrn a in3 vrp a in2 a vss a vdd a in1 a vss dvdd dvss nsig dvalid_f vd_f hd data7 data6 data5 dvss dtclk pvdd1 data4 data3 data2 data1 pdn rstn oe sela scl pvdd2 sda dvss dvdd test1 test0 data0
[AK8853XQ/ vn] rev-e-00 4 2008/01 3. pin functions pin no. symbol p/s 1 i/o 2 description 1 vrn a o internal reference negative vo ltage pin for ad converter. connect to avss via 0.1 f ceramic capacitor. 2 ain3 a i analog video signal input pin. co nnect via 0.033 f capacitor and voltage-splitting resistors as shown in sec. 11. 3 vrp a o internal reference positive vo ltage pin for ad converter. connect to avss via 0.1 f ceramic capacitor. 4 ain2 a i analog video signal input pin. co nnect via 0.033 f capacitor and voltage-splitting resistors as shown in sec. 11. 5 avss a g analog ground pin. 6 avdd a p analog power supply pin. 7 ain1 a i analog video signal input pin. co nnect via 0.033 f capacitor and voltage-splitting resistors as shown in sec. 11. 8 avss a g analog ground pin. 9 dvdd d p digital power supply pin. 10 dvss d g digital ground pin. 11 nsig p1 o shows status of synchronization with input signal. low: signal present (synchronized). high: signal not present or not synchronized. see table below for relation of output to oe, pdn, rstn pin status. 12 dvalid_ f p1 o (i/o) dvalid/field signal output pin. dvalid and field output signals sw itched by register setting. used as i/o pin in test mode. see table below for relation of output to oe, pdn, rstn pin status. 13 vd_f p1 o vertical timing/ field timing signal output pin. vd and field output signals switched by register setting. see table below for relation of output to oe, pdn, rstn pin status. 14 hd p1 o (i/o) horizontal timing signal output pin. used as i/o pin in test mode. see table below for relation of output to oe, pdn, rstn pin status. 15 data7 p1 o (i/o) data output pin. (msb) used as i/o pin in test mode. see table below for relation of output to oe, pdn, rstn pin status. 16 data6 p1 o (i/o) data output pin. used as i/o pin in test mode. see table below for relation of output to oe, pdn, rstn pin status. 17 data5 p1 o (i/o) data output pin. used as i/o pin in test mode. see table below for relation of output to oe, pdn, rstn pin status. 18 dvss d g digital ground pin. 19 dtclk p1 o data clock output pin. approx. 27 mhz clock output. see table below for relation of output to oe, pdn, rstn pin status. 20 pvdd1 p1 p i/o power supply pin. 21 data4 p1 o (i/o) data output pin. used as i/o pin in test mode. see table below for relation of output to oe, pdn, rstn pin status. 1 power supply: a, avdd; d, dvdd; p1, pvdd1; p2, pvdd2. 2 input/output: o, output pin; i, intput pin; i/o, input/output pin; p, power supply pin; g, ground connection pin.
[AK8853XQ/ vn] rev-e-00 5 2008/01 pin no. symbol p/s 1 i/o 2 description 22 data3 p1 o (i/o) data output pin. used as i/o pin in test mode. see table below for relation of out put to oe, pdn, rstn pin status. 23 data2 p1 o (i/o) data output pin. used as i/o pin in test mode. see table below for relation of out put to oe, pdn, rstn pin status. 24 data1 p1 o (i/o) data output pin. used as i/o pin in test mode. see table below for relation of out put to oe, pdn, rstn pin status. 25 data0 p1 o (i/o) data output pin. used as i/o pin in test mode. see table below for relation of out put to oe, pdn, rstn pin status. 26 test0 d i pin for test mode setting. connect to dvss. 27 test1 d i pin for test mode setting. connect to dvss. 28 dvdd d p digital power supply pin. 29 dvss d g digital ground pin. 30 sda p2 i/o i 2 c data pin. connect to pvdd2 via a pull-up register. hi-z input possible when pdn=l. will not accept sda input during reset sequence. 31 pvdd2 p2 p microprocessor i/f power supply pin. 32 scl p2 i i 2 c clock input pin. use pvdd2 or lower for input. hi-z input possible when pdn=l. will not accept scl input during reset sequence. 33 sela p2 i i 2 c bus address selector pin. pvdd2 connection: slave address [0x8a] dvss connection: slave address [0x88] 34 oe p2 i output enable pin. l: digital output pin in hi-z output mode. h: data output mode. hi-z input to oe pin is prohibited. 35 rstn p2 i reset signal input pin. hi-z input is prohibited. l: reset. h: normal operation. 36 pdn p2 i power-down control pin. hi-z input is prohibited. l: power-down. h: normal operation. 37 clkmd d i clock mode selection pin. connect to dvdd or dvss. dvss connection: for crystal. dvdd connection: for quartz gener ator or other external clock input; not for crystal. 38 dvdd d p digital power supply pin. 39 xti d i crystal connection pin. connect to digital ground via 22 pf c apacitor as shown in sec. 11. use 24.576 mhz crystal resonator. for input from 24.576 mhz crysta l oscillator, use this pin. 1 power supply: a, avdd; d, dvdd; p1, pvdd1; p2, pvdd2. 2 input/output: o, output pin; i, intput pin; i/o, input/output pin; p, power supply pin; g, ground connection pin.
[AK8853XQ/ vn] rev-e-00 6 2008/01 pin no. symbol p/s 1 i/o 2 description 40 dvss d g digital ground pin. 41 xto d o crystal connection pin. connect to digital ground via 22 pf capacitor as shown in sec. 11. use 24.576 mhz crystal. when pdn=l, output level is dvss. if crystal is not used, connect to nc or dvss. 42 avss a g analog ground pin. 43 avdd a p analog power supply pin. 44 iref a o reference current setting pin. connect to ground via 6.8 k ? ( 1% accuracy) resistor. 45 avss a g analog ground pin. 46 atio a i/o analog test pin. for normal operation, connect to avss. 47 vcom a o common internal voltage for ad convertor. connect to avss via 0.1 f ceramic capacitor. 48 ain4 a i analog video signal input pin. connect via 0.033 f capacitor and voltage-splitting resistors as shown in sec. 11. 1 power supply: a, avdd; d, dvdd; p1, pvdd1; p2, pvdd2. 2 input/output: o, output pin; i, intput pin; i/o, input/output pin; p, power supply pin; g, ground connection pin. output pin status as determined by oe, pdn, and rstn pin status. oe pdn rstn output1 1 output2 1 l x x hi-z output l output h l x l output l output l l output l output h h h default data out 2 default data out 2 1 output1: data[7:0], hd, vd_f, dvalid_f, dtclk output2: nsig if oe=h and pdn=h just after power is tur ned on, output pin status will be indefinite until internal state is determined by reset sequence. 2 in the absence of ain signal input, output will be black data ((y=0x10, cb/cr=0x80). (blueback output can be obtai ned by register setting.)
[AK8853XQ/ vn] rev-e-00 7 2008/01 4. electrical specifications 4.1 absolute maximum ratings parameter min max units notes supply voltage dvdd, avdd pvdd1 , pvdd2 ? 0.3 ? 0.3 2.2 4.2 v v ? analog input pin voltage a (vina) ? 0.3 avdd + 0.3 ( 2.2) v ? digital input pin voltage d (vind) ? 0.3 dvdd + 0.3 ( 2.2) v xti, xto, clkmd, test0, test1 digital output pin voltage p1 (voutp) ? 0.3 pvdd1 + 0.3 ( 4.2) v dtclk, data[7:0], hd, vd_f, dvalid_f, nsig digital input pin current p2 (vinp) ? 0.3 pvdd2 + 0.3 ( 4.2) v oe, sela, pdn, rstn, sda, scl input pin current (iin) (except for power supply pin) ? 10 10 ma ? storage temperature ? 40 125 ? c ? the above supply voltages are referenced to ground pins (dvss= avss) at 0 v (the reference voltage). all power supply grounds (avss, dvss) shoul d be at the same electric potential. if digital output pins are connect ed to data bus, the data bus operat ing voltage should be in the same range as shown above for the digital output pin. 4.2 recommended operating conditions parameter min typ max units condition analog supply voltage (avdd) digital supply voltage (dvdd) 1.70 1.80 2.00 v avdd=dvdd i/o supply voltage (pvdd1) mpu i/f supply voltage (pvdd2) 1.70 1.80 3.60 v pvdd1 dvdd pvdd2 dvdd ? 40 ? 105 ? c AK8853XQ operating temp. (ta) ? 40 ? 85 ? c ak8853vn the above supply voltages are referenced to ground pins (dvss= avss) at 0 v (the reference voltage). all power supply grounds (avss, dvss) shoul d be at the same electric potential.
[AK8853XQ/ vn] rev-e-00 8 2008/01 4.3 dc characteristics where no specific condition is indicated in the following table, t he supply voltage range is the same as that s hown for the recommended operati ng conditions in 4-2 above. parameter symbol min typ max units condition 0.8pvdd2 ? ? v case 1 a digital p2 input high voltage vih 0.7pvdd2 ? ? v case 2 b ? ? 0.2pvdd2 v case 1 a digital p2 input low voltage vil ? ? 0.3pvdd2 v case 2 b digital d input high voltage vdih 0.8dvdd ? ? v ? digital d input low voltage vdil ? ? 0.2dvdd v ? digital input leak current il ? ? 10 ua ? digital output high voltage voh 0.7pvdd1 ? ? ? ioh = ? 600ua digital output low voltage vol ? ? 0.3pvdd1 ? iol = 1ma i 2 c (sda)l output volc ? ? 0.3 pvdd2 v iolc = 3ma a dvdd = 1.70v~2.00v, 1.70v pvdd1<2.70v, 1.70v pvdd2<2.70v, ta: recommended operating temp. b dvdd = 1.70v~2.00v, 2.70v pvdd1 3.60v, 2.70v pvdd2 3.60v, ta: recommended operating temp. definition of above input/output terms digital p2 input: collective term for sda, scl, sela, oe, pdn, rstn pin inputs. digital d input: collective term fo r clkmd, test0, test1 pin inputs. digital output: collective term for dtclk, da ta[7:0], hd, vd_f, dvalid_f, nsig pin outputs. sda pin output: not termed digital pin output unless otherwise specifically stated.
[AK8853XQ/ vn] rev-e-00 9 2008/01 4.4 analog characteristics (avdd=1.8v, temp.25 ? c) selector clamp parameter symbol min typ max units condition maximum input range vimx 0 0.50 0.60 v pp max value at minimum pga_gain setting pga parameter symbol min typ max units resolution ? 7 ? bits minimum gain gmn ? ? 6 ? db maximum gain gmx ? 6 ? db gain step gst ? 0.094 0.235 db ad converter parameter symbol min typ max units condition resolution res 10 bits ? operating clock frequency fs ? 27 ? mhz ? integral nonlinearity inl ? 1.0 3.0 lsb fs = 27 mhz, pga_gain default setting differential nonlinearity dnl ? 0.5 1.5 lsb fs = 27 mhz, pga_gain default setting s/n sn ? 53 ? db fin = 1 mhz*, fs = 27 mhz, pga_gain default setting s/(n+d) snd ? 51 ? db fin=1mhz*, fs=27mhz pga_gain default setting adc internal common voltage vcom ? 0.9 ? v ? adc internal positive vref vrp ? 1.1 ? v ? adc internal negative vref vrn ? 0.7 ? v ? *fin = ain input signal frequency aaf (anti-aliasing filter) parameter symb ol min typ max units condition pass band ripple gp ? 1 +1 db 6 mhz stop band blocking gs 10 22 ? db 27 mhz 4.5 current consumption ( at dvdd = avdd = pvdd1 = pvdd2 = 1.8v, ta = recommended operating temp. ) parameter symbol min typ max units condition (active mode) total analog block digital block i/o block idd aidd didd pidd 58 35 19 4 76 ma ma ma ma a with crystal connected load condition: cl=15pf (power down mode) total analog block digital block i/o block sidd asidd dsidd psidd 1 1 1 1 200 ua ua ua ua a with ntsc-j 100% color bar input.
[AK8853XQ/ vn] rev-e-00 10 2008/01 4.6 crystal circuit block (ta: recommended operating temp.) parameter symbol min typ max units notes frequency f 0 ? 24.576 ? mhz ? frequency tolerance f/f ? 100 ppm ? load capacitance cl ? 15 ? pf ? effective equivalent resistance re ? ? 100 ? see note 1 crystal parallel capacitance co ? 0.9 ? pf ? xti terminal external connection load capacitance cxi ? 22 ? pf if cl=15 pf xto terminal external connection load capacitance cxo ? 22 ? pf if cl=15 pf (note1) effective equivalent resistance general ly may be taken as re = r1 x (1+co/cl) 2 , where r1 is the crystal se ries equivalent resistance. example connection xti pin xto pin rf rd ( note2 ) cxi = 22pf cxo = 22pf a k8853 internal circuit external circuit (note2) determine need for and appropriate value of limiting resistance (rd) in accordance with the crystal specifications.
[AK8853XQ/ vn] rev-e-00 11 2008/01 5. ac timing (dvdd=1.70v~2.00v, pvdd1=pvdd2=1.70v ~3.60v, recommended operating temp.) load condition: cl=15pf 5.1 clock input set ak8853 clock input as follows. fclk tclkl tclkh 0.8dvdd 1/2 level 0.2dvdd parameter symbol min typ max units input clk fclk ? 24.576 ? mhz clk pulse width h tclkh 16 ? ? ns clk pulse width l tclkl 16 ? ? ns frequency tolerance ? ? ? 100 ppm 5.2 clock output (dtclk output) parameter symbol min typ max units dtclk fdtclk ? 27 ? mhz fdtclk 0.5pvdd1
[AK8853XQ/ vn] rev-e-00 12 2008/01 5.3 output data (data[7:0], hd, vd_f, dvalid_f) timing tds 0.5pvdd1 tdh voh vol dtclk output data parameter symbol min typ max units output data setup time tds 10 nsec output data hold time tdh 10 nsec 5.4 register reset timing resettiming rstn fclk vil parameter symbol min typ max units notes rstn pulse width resettiming 100 (4.1) ? ? clk (sec) based on clock leading edge note. clock input is necessa ry for reset operation. rstn pin must be pulled low following clock application.
[AK8853XQ/ vn] rev-e-00 13 2008/01 5.5 power-down sequence and reset sequence after power-down reset must be applied for at least 2048 clock cycl es (or 83.33 s) before setting pdn (pdn=low). reset must be applied for at least 10 ms after pdn release (pdn=hi). vih vil vih clkin rstn pdn ress resh gnd parameter symbol min typ max units reset width before setting pdn ress 2048 (83.33) ? ? clk (s) reset width after pdn release resh 10 ? ? ms to perform power-down, all control signals must alwa ys be brought to the volt age polarity to be used or to ground level. for any power supply removal, all power supplies must be removed. clock input is necessary for resetting. the power-down sequence for connection of the crystal is as follows. a vdd/dvdd pvdd1/pvdd2 pdn rstn 5 ms (max) to stable crystal oscillation* xti vcom,vrp,vrn pdn release * reference value resh 10ms(min)
[AK8853XQ/ vn] rev-e-00 14 2008/01 5.6 power-on reset at power-on, reset must be applied until the analog reference voltage and current have stabilized. 1 avdd/dvdd/pvdd1/pvdd2 should be raised simultaneously at power-on. 2 vil respon vref rstn vdd parameter symbol min typ max units rstn pulse width respon 10 ms 1 clock input is necessary for resetting. 2 if not simultaneous, then raise in the order pvdd2 -> avdd/dvdd -> pvdd1.
[AK8853XQ/ vn] rev-e-00 15 2008/01 5.7 i 2 c bus input timing ( dvdd=1.70v~2.00v, pvdd1=pvdd2=1.70v~3.60v, recommended operating temp. ) 5.7.1 timing 1 tbuf thd : sta tr tf tsu : sto vih vil sda tf tr tsu : sta tlow vih vil scl parameter symbol min max units bus free time tbuf 1.3 usec hold time (start condition) thd:sta 0.6 usec clock pulse low time tlow 1.3 usec input signal rise time tr 300 nsec input signal fall time tf 300 nsec setup time(start conditi on) tsu:sta 0.6 usec setup time(stop condition) tsu:sto 0.6 usec note. the timing relating to the i 2 c bus is as stipulated by the i 2 c bus specif ication, and not determined by the device itself. for details, see i 2 c bus specif ication. 5.7.2 timing 2 vih vil sda vih vil scl thigh thd : dat tsu : dat parameter symbol min typ units data setup time tsu:dat 100 1 nsec data hold time thd:dat 0.0 0.9 2 usec clock pulse high time thigh 0.6 usec 1 if i 2 c is used in standard mode, tsu: dat 250 ns is required. 2 this condition must be met if the ak8853 is used wi th a bus that does not extend tlow (to use tlow at minimum specification).
[AK8853XQ/ vn] rev-e-00 16 2008/01 6. functional overview the following key functions are characterist ic of the ak8853 and its operational performance. (1) it accepts composite video signal (cvbs) input, with 4 input pins availabl e for this purpose. the decode signal is selected via the register. (2) it contains an internal analog ban d limiting filter (anti-aliasing) in front of the ad converter input. (3) its analog circuit clamps the input signal to the sy nc tip (analog sync tip clamp). its digital circuit clamps the digitized input data to the pedestal level (digital pedestal clamp). (4) it decodes ntsc-m, ? j; ntsc-4.43; pal-b, d, g, h, i, n; pal-nc, pal-m, pal-60; and secam video signals, as selected by register setting for input signal category. in auto detection mode, it automatically recognizes t he input signal category. (5) its vbi data slicing function enabl es output of the slicing results as itu-r bt.601 format digital data. (6) its adaptive agc function enables measurement of the input signal size and determination of the input signal level. (7) its acc function enables measurem ent of the input signal color bur st size and determination of the appropriate color burst level. (8) it performs adaptive two-dimensional y/c separat ion, in which its phase detector selects the best correlation from among vertical, horizontal, and diagonal samples and the optimum y/c separation mode. (9) its digital pixel spacing adjus tor can align vertical positions by vertical pixel positioning. (10) it operates in line-locked, frame-locked, or fix ed clock mode, with automat ic transition and optimum mode selection by automatic scanning. (11) in pal-b, d, g, h, i, and n decoding, it c an perform phase-difference correction for each line. (12) its decoded data is itu-r bt.656 compliant, except in certain cases of fixed-clock operation or poor-quality input signal. (13) for connection of devices havi ng no itu-r bt.656 interface, it shows the active video region by dvalid signal output. (14) its input-stage embedded pga c an be adjusted in the range -6~+6db by register setting, in gain steps of approximat ely 0.1 db/step. (15) it detects and separat es the sync signal from the digitiz ed input signal. the det ected sync signal provides the base timing for decode processing, and t he separated sync signal as the basis for calculation of phase error signal and for sampling clock control. (16) it judges the chroma signal quality from the color burst of the input signal, and can apply color kill if the signal quality is judged insufficient. it can also apply color kill if the color decode pll lock is lost. (17) its image quality adjustment function includes contrast, bri ghtness, hue, color saturation, and sharpness adjustment. (18) its luminance band limiting filter is adjustable via register setting. (19) it can provide sepia output of decoded results. (20) it can decode conflated clos ed caption data, clos ed caption extended data, vbid(cgms), and wss signals, and write them separ ately to the storage register. (21) its monitoring register enables moni toring of a number of internal functions. (22) it enables macrovision signal ty pe notification, in cases where t he macrovision signal is included in the decoded data. (23) it enables u/v signal band adjustment, by switchin g the low pass filter af ter c signal demodulating. (24) it enables c filter band switching vi a the register, for y/c separation.
[AK8853XQ/ vn] rev-e-00 17 2008/01 7. functional description 7.1 analog interface the ak8853 accepts composite video signal (cvbs) input, wi th 4 input pins available for this purpose. the decode signal is sele cted via the register. insel[1:0]-bits input channel selection notes [00] ain1 [01] ain2 [10] ain3 [11] ain4 7.2 analog band limiting filter and analog clamp circuit 7.2.1 analog band limiting filter the characteristics of the ak8853 internal analog band limit ing filter (anti-aliasing), which is in front of the ad converter input, are as follows: 1db (~6mhz ) ? 22db (27mhz)?.typical value 7.2.2 analog clamp circuit the analog circuit of the ak8853 clamps the input signal to the sync ti p (analog sync tip clamp). the clamp timing pulse, with its origin at the falling ed ge of the internally synchronized and separated sync signal, is generated at approximately t he central position of the sync signal . its digital circuit clamps the digitized input data to the pedestal level (digital pedestal clamp), as described in sec. 7.20 below. 7.3 input video signal categorization the ak8853 can decode the following video signals, in accordance with the register setting. ntsc-m,j ntsc-4.43 pal-b,d,g,h,i,n pal-nc pal-m pal-60 secam in auto detection mode, it automatically recognizes the input signal category, from among the above.
[AK8853XQ/ vn] rev-e-00 18 2008/01 the register settings for the input signal c haracterization are essentially as follows. vscf[1:0]-bits: setting for subca rrier frequency of input signal. vscf[1:0]-bits subcarrier frequency (mhz) formats [00] 3.57954545 ntsc-m,j [01] 3.57561149 pal-m [10] 3.58205625 pal-nc [11] 4.43361875 pal-b, d, g, h, i, n, ntsc-4.43, pal-60, secam* *for secam input signal, set vscf[1:0] to [11]. vcen[1:0]-bits: setting for color encode format of input signal. vcen[1:0]-bits color encode format notes [00] ntsc [01] pal [10] secam [11] reserved vlf-bit: setting for line frequency of each input frame. vlf-bit number of lines notes [0] 525 ntsc-m, j, ntsc-4.43, pal-m, pal-60 [1] 625 pal-b, d, g, h, i, n, nc, secam bw-bit: setting for decoding of input signal as monochrome signal (monochrome mode) bw-bit signal type [0] not monochrome (monochrome mode off) [1] decode as monochrome si gnal (monochrome mode on) in the monochrome mode, the input signal is tr eated as a monochrome signal, and all sampling data digitized the the ad converter passes through the luminance process and is pr ocessed as a luminance signal. thus, with this bit on, the signal input to the y/c separation block is all output as luminance signal data to the luminance signal processing block. in the monochrome mode, the cbcr code is output as 0x80 (601 leve l data) regardless of the input. setup-bit: setting for presence or absence of input signal setup. setup-bit setup presence/absence notes [0] setup absent ? [1] setup present 7.5ire setup with the setup present setting, the luminance and color signals are processed as follows: luminance signal: y=(y-7.5)/0.925 color signal: u=u/0.925, v=v/0.925
[AK8853XQ/ vn] rev-e-00 19 2008/01 the register settings for auto detec tion are essentially as follows. autodet-bit: settings for auto detection of input signal (auto detection mode) autodet-bit auto detection notes [0] off manual setting [1] on ? the auto detection recognizes the following parameters. number of lines per frame: 525/625 carrier frequencies: 3.57954545 3.57561149 3.58205625 4.43361875 color encoding formats: ntsc pal secam monochrome signal: not monochrome/monochrome note: automatic monochrome detection is active if the color kill setting is on (colkill-bit = [1].) the ak8853 stores the detec ted parameter to the i nput video status register (thus, as an internal notice function). this enables the host to distinguish among the formats ntsc-m, j; ntsc -4.43; pal-b, d, g, h, i, n; pal-m; pal-nc; pal-60; secam; and monochrome. it should be noted that it does not detect ntsc-m, ntsc-j, or pal-b , d, g, h, i, n formats. in auto detection, the candidates for detection can be limited as shown below. ndmode register: for limiti ng auto detecti on candidates bit register name r/w definition bit 0 ndpalm no detect pal-m bit r/w [0]: pal-m candidate [1]: pal-m non-candidate bit 1 ndpalnc no detect pal-nc bit r/w [0]: pal-nc candidate [1]: pal-nc non-candidate bit 2 ndsecam no detect secam bit r/w [0]: secam candidate [1]: secam non-candidate bit 3 reserved reserved r/w reserved bit 4 ndntsc443 no detect ntsc-4.43 bit r/w [0]: ntsc-4.43 candidate [1]: ntsc-4.43 non-candidate bit 5 ndpal60 no detect pal-60 bit r/w [0]: pal-60 candidate [1]: pal-60 non-candidate bit 6 nd525l no detect 525line bit r/w [0]: 525 line candidate [1]: 525 line non-candidate bit 7 nd625l no detect 625line bit r/w [0]: 625 line candidate [1]: 625 line non-candidate
[AK8853XQ/ vn] rev-e-00 20 2008/01 in making the above register settings , the following restrictions apply, 1. setting both ndntsc443(bit 4) and ndpal60( bit 5) to [1] (high) is prohibited. 2. setting both nd525l(bit 6) and nd625l( bit 7) to [1] (high) is prohibited. 3. to limit candidate formats, it is necessary to have the auto detection mode off while first setting the register to non-limited signal status and next the ndmode settings, and then setting the auto detection mode to on. set auto detection mode to off set input video standard register to non-limited signal status enter ndmode register settings set auto detection mode to on 7.4 output data format in the ak8853, the settings for t he output code and the vert ical blanking interval s for the output signal are as follows. vbil[2:0]-bits: settings for vertical blanking interval vbil[2:0]-bits 525/625 lines vertical blanking interval notes 525 line1~line20 and line263.5~line283.5 [001] 625 line623.5~line23 and line311~line336.5 +1line 525 line1~line21 and line263.5~line284.5 [010] 625 line623.5~line24 and line311~line337.5 +2lines 525 line1~line22 and line263.5~line285.5 [011] 625 line623.5~line25 and line311~line338.5 +3lines 525 line1~line19 and line263.5~line282.5 [000] 625 line623.5~line22 and line311~line335.5 default 525 line1~line16 and line263.5~line279.5 [101] 625 line623.5~line19 and line311~line332.5 -3lines 525 line1~line17 and line263.5~line280.5 [110] 625 line623.5~line20 and line311~line333.5 -2lines 525 line1~line18 and line263.5~line281.5 [111] 625 line623.5~line21 and line311~line334.5 -1line [100] reserved reserved ? as indicated in this table, t he default values are lines 1~19 and 263.5~282.5 for 525-line signals and lines 623.5~22 and 311~335.5 for 625-li ne signals, and other specific va lues are set by entering the difference from these default values.
[AK8853XQ/ vn] rev-e-00 21 2008/01 601limit-bit: settings for output data code min/max 601limit-bit output data code min~max notes [0] y: 1~254 cb, cr: 1~254 default [1] y: 16~235 cb, cr: 16~240 the ak8853 data code output form at (y:cb:cr=4:2:2) is compliant with itu-r bt.601. all internal calculating operations are made with min = 1, max = 254. with 601limit-bit set to [1], codes 1~15 and 236~254 are respectively clipped to 16,235. trsvsel-bit: settings for v-bit handling in itu-r bt.656 format 525-line 625-line trsvsel-bit v-bit=0 v-bit=1 v-bit=0 v-bit=1 [0] itu-r bt 656-3 compliant line10~line263 line273~line525 line1~line9 line264~line272 [1] itu-r bt 656-4 smpte125m compliant line20~line263 line283~line525 line1~line19 line264~line282 line23~line310 line336~line623 line1~line22 line311~line335 line624~line625 these values are unaffected by the vbil[2:0]-bits setting. sllvl-bit: settings for slice level sllvl-bit slice level [0] 25ire [1] 50ire the results of vbi slicing by t he ak8853 slicing function ar e output as itu-r bt. 601 digital data. the vbi interval is set via vbil[2:0]- bits. vbi slicing is performed in the luminance signal processing path, so that the cb/cr value of the effective line 601 output code is output at the same level as the corresponding luminance signal. the slice level and the output code are set via the register. the out put code value is set via the hi/low slice data set register, as follows. hi slice data set register*: setting for higher of two values resulting from slicing. default: 0xeb(235) low slice data set register*: setting for lowe r of two values resulting from slicing. default: 0x10(16) *note that a setting of 0x00 or 0xff corresponds to a special 601 code. vbidec[1:0]-bits: settings fo r decode data in the vbi period vbidec[1:0]-bits decode data notes [00] black level output y = 0x10 cb/cr = 0x80 [01] monochrome mode y = data converted to 601 level cb/cr = 0x80 [10] sliced data output during vbi y/cb/cr = value corresponding to slice level (value set at hi/low slice data set register) [11] reserved reserved note that, with vbi period settings of lines 1~ 9 and 263.5~272.5 in the 525 line and lines 623.5~6.5 and 311~318 in the 625 line, the setting vbidec[1:0] will not be enter ed and the output will be in black level code.
[AK8853XQ/ vn] rev-e-00 22 2008/01 (mv*) ntsc/pal 601 code 714/700 235 357/350 180/175 *threshold values (mv) are approximate. 127 63 100% white 50ire threshold with setting sllvl = [1] 25ire threshold with setting sllvl = [0] ```` l l l ```` l l h h h h cb/y cr/y `````` cb/y `````` cr/y l: h: value set by high slice data set register value set by low slice data set re g iste r ````` ``````` high/low conversion is performed for ei ther the cb/y or the cr/y comb ination. the above figure is an example of the conversion points for cb/y. 7.5 output pin status for normal operation, the output fr om the data[7:0], vd_f, dvalid_f, nsig, and hd pins can each be fixed at low via the output c ontrol register. note, however, that the oe, pdn, and rstn pin states will have priority regardl ess of these register settings. 7.6 vlock mechanism the ak8853 synchronizes internal operation with the input signal frame structure. if, for example, the frame structure of the input signal comprises 524 lines, the internal operation w ill have a structure of 524 lines per frame. this mechanism is termed the vlock mechanism. if an input signal changes from a structure of 525 lines per frame to one of 524 lines per frame, internal operation will ch ange accordingly, and the vlock mechanism will go to unlock via a pull-in process. in such case, the unlock status can be confirmed via the control regi ster [vlock-bit]. note that t he time required for locking of the vlock mechanism upon channel or other input signal switching will be about 4 frames.
[AK8853XQ/ vn] rev-e-00 23 2008/01 actsta[2:0]-bits: adjustment of active video start position actsta[2:0]-bits line and active video start approximate delay/advance (ns) 525 line 124 th sample [001] 625 line 134 th sample 74, delay 525 line 125 th sample [010] 625 line 135 th sample 148, delay 525 line 126 th sample [011] 625 line 136 th sample 222, delay 525 line 123 th sample [000] 625 line 133 th sample default value (normal position) 525 line 120 th sample [101] 625 line 130 th sample 222, advance 525 line 121 th sample [110] 625 line 131 th sample 148, advance 525 line 122 th sample [111] 625 line 132 th sample 74, advance [100] reserved reserved ? with the default value, the star t position is as follows (with itu-r bt.601 format compliance). 122samples(525line) a ctive video start o h 132samples(625line) a ctive video start o h 7.7 auto gain control_agc the agc of the ak8853 measures the size of the input sync signal (i.e., the difference between the sync tip and pedestal levels), and adjusts the pga va lue to bring the sync signal level to 286 a or 300 b mv. the agc function amplifies the input signal to t he appropriate size and enables input to the ad converter. the agc function in the ak8853 is adaptive, and thus incl udes peak agc as well as sync agc. peak agc is effective for input signals in which the sync signal level is appropriate and only the active video signal is large. a ntsc-m, j; ntsc-4.43; pal-m b pal-b, d, g, h, i, n; pal-nc; pal-60; secam agct[1:0]-bits: settings for agc time constant agct[1:0]-bits time constant notes [00] disable agc off, pga register enabled. [01] fast t= 1field [10] middle t= 7fields [11] slow t= 29fields t is the time constant. manual setting of the pga register is possible only if agc is disabled.
[AK8853XQ/ vn] rev-e-00 24 2008/01 agcc-bit: settings for agc non-sensing range agcc[1:0]-bits non-sensing range notes [00] 2lsb ? [01] 3lsb ? [10] 4lsb ? [11] none ? agcfrz-bit: settings for freezing agc function agcfrz-bit agc status notes [0] non-frozen ? [1] frozen ? note. the gain value at the time of freezing is maintained during the froz en state, and it is then possible to read out the gain value via the pga1,2 control register. agctl-bit: settings for selection of quick or slow transition between peak and sync agc agctl-bit agc transition notes [0] quick ? [1] slow ? 7.8 auto color control_acc the acc of the ak8853 measur es the level of the input signal co lor burst, and adjusts the level to 286 a or 300 b mv, as appropriate. the acc is not applicabl e to secam. as in agc, both acc time constant and acc freeze settings can be entered. a ntsc-m,j, ntsc-4.43, pal-m b pal-b, d, g, h, i, n, pal-nc, pal-60 acct[1:0]-bits: settings for acc time constant acct[1:0]-bits time constant notes [00] disable acc off [01] fast t= 2fields [10] middle t= 8fields [11] slow t= 30fields accfrz-bit: settings fo r freezing acc function accfrz-bit acc status notes [0] non-frozen ? [1] frozen ? note. the burst-level setting at the time of freezing is maintained dur ing the frozen state. the acc and color saturation functions operate indepen dently. if acc is enabled, the color saturation adjustment is applied to the signal that has been adjusted to the appropriate level by the acc.
[AK8853XQ/ vn] rev-e-00 25 2008/01 7.9 y/c separation the adaptive two-dimensional y/c se paration of the ak8853 utilizes a co rrelation detector to select the best-correlated direction from among vertical, horizontal, and di agonal samples, and selects the optimum y/c separation mode. fo r ntsc-4.43, pal-60, and secam inputs, the y/c separation is one-dimensional only, regardless of the setting. ycsep[1:0]-bits: settings for y/c separation method ycsep[1:0]-bits y/c separation mode notes [00] adaptive selects [01] or [ 10] setting, as appropriate [01] 1-d 1d (bpf) [10] 2-d ntsc-m, j, pal-m: 3 line 2-d pal-b, d, g, h, i, n, nc: 5 line 2-d [11] reserved ? for ntsc-4.43, pal-60, and secam inputs, y/c separ ation is 1-d only, regardless of the setting. 7.10 c filter the bandwidth of the c f ilter can be set via the register, as follows. c358fil[1:0]: settings for c f ilter bandwidth, for input signal with 3.58 mhz subcarrier wave c358fil[1:0] -bits notes notes [00] narrow [01] medium [10] wide [11] reserved ntsc-m, j, pal-m, pal-nc c443fil[1:0]: settings for c f ilter bandwidth, for input signal with 4.43 mhz subcarrier wave c443fil[1:0] -bits notes notes [00] narrow [01] medium [10] wide [11] reserved pal-b, d, g, h, i, n, ntsc-4.43, pal-60 note. no bandwidth selection is possible for secam input. 7.11 uv filter the uv bandwidth can be changed by switching betw een two low pass filter types for the demodulated c signal. uvfilsel-bit: settings fo r uv filter switching uvfilsel -bit bandwidth notes [0] wide [1] narrow
[AK8853XQ/ vn] rev-e-00 26 2008/01 7.12 digital pixel interpolator the digital pixel interpolator of the ak8853 aligns vertical pixel positions in both frame-lock and fixed-clock operating modes. the pixel interpolator c an be set to on or off via the register. with a register setting of auto, the pixel interpolator is off or on depending on the clock mode, as follows. line-locked clock mode off frame-locked clock mode on fixed-clock mode on intpol[1:0]-bits: settings for pixel interpolator operation intpol[1:0]-bits interpolator operation notes [00] auto dependent on clock mode. [01] on ? [10] off ? [11] reserved ? 7.13 clock generation the ak8853 operates in the following three clock modes. 1. line-locked clock mode the ?line-locked clock? is generated by pll usi ng the horizontal sync si gnal within the input signal. if no input signal is present, the ak8853 w ill switch from this m ode to fixed-clock mode. 2. frame-locked mode the ?frame-locked clock? is generated by pll us ing the vertical sync signal within the input signal. if no input signal is present, the ak8853 w ill switch from this m ode to fixed-clock mode. 3. fixed-clock mode no pll control is applied in this mode, which is enabled only when eith er it is set via the register or no input signal is present. in this mode, data capture cannot be pe rformed in eav (end active video), and must be performed in sav (start active video) format. the number of pixels per line is not guaranteed in this mode, but data guarantee is perfo rmed in the interval from sav to eav. the ak8853 transition functi on automatically switches among the above modes and selects the optimum one, and when no input signal is present switches to the fixed-clock mode. in the line-locked and frame-locked clock modes, the cl ock is synchronized with the input signal and the output is thus itu-r bt.656 compliant. it shou ld be noted, however, that itu-r bt.656-compliant output may not be possible with low-quality input signals. it should also be noted that in the fixed-clock mode the sample number will be insufficient for itu-r bt.656 compliance, due to non-sync hronization of the input data. clkmode[1:0]-bits: settings for selection of clock generation mode clkmode[1:0]-bits clock generation mode notes [00] automatic ? [01] line-locked ? [10] frame-locked ? [11] fixed-clock ?
[AK8853XQ/ vn] rev-e-00 27 2008/01 7.14 phase correction in pal-b, d, g, h, i, n, nc, 60, and m decoding, the ak8853 performs phase correction for each line. with this function on, color averaging is performed for each line. in the adapt ive phase correction mode, interline phase correlation is sampled and color averaging is performed for correlated samples. interline color averaging is also performed in ntsc-m and j decoding. no phase correction or color averagi ng is performed in secam decoding. dpal[1:0]-bits: settings for phase correction dpal[1:0]-bits status notes [00] adaptive phase correction mode ? [01] phase correction on ? [10] phase correction off ? [11] reserved ? 7.15 no-signal output if no input signal is found (as shown by the control bit nosig-bit), the out put signal is black-level, blue level (blueback), or input-state (sands torm), depending on the register setting. nsigmd-bits: settings for output signals for no input signal nsigmd [1:0]-bits output notes [00] black-level ? [01] blue-level (blueback) ? [10] input-state (sandstorm) ? [11] reserved ?
[AK8853XQ/ vn] rev-e-00 28 2008/01 7.16 output interface 7.16.1 656 interface 7.16.1.1 line-locked and frame-locked clock modes in both of these modes, the decoded data output is compliant with itu-r bt.656, which requires the following sample and line numbers. samples per line: 858 (525 line) or 864 (625 line) lines per frame: 525 or 625 it may not be possible, however, to meet these requirements if the input signal quality is poor. in the ak8853, pll is locked to the input signal and output-stage buffers absorb input signal jitter, but if the jitter is excessive pll tracking may be imprac ticable and itu-r bt.656 compliance may thus be lost. in such cases, the following processing can be applied via the indica ted register settings. (a) line drop/repeat processing a line drop or line repeat will result in output signals with 524/624 or 526/626 lines per frame, respectively. line drop/repeat processing ma y be performed at any line in the frame. (b) pixel drop/repeat processing a pixel drop or pixel repeat will result in output signals less or more than the required 858/864 samples in the last line of t he frameor field, respectively. note: in the event of output-stage buffer failu re, line drop/repeat processing will be performed even if the register setting is for pixel drop/repeat processing. errhnd-bits: settings for line and pixel drop/repeat processing errhnd-bits processing mode notes [00] line drop / line repeat default [01] pixel drop / pixel repeat by field ? [10] pixel drop / pixel repeat by frame ? [11] reserved ?
[AK8853XQ/ vn] rev-e-00 29 2008/01 7.16.1.2 fixed-clock mode in fixed-clock mode, operation is at an internally generated 27 mhz clock, from a 24.576 mhz input clock. the output signal is therefore not sy nchronized with the input signal, and thus not itu- bt.656 compliant. data is output in sav format. as shown in the following figure, eav is guarant eed for 720 pixels from sav, but the sample number from eav to sav is not. 858 / 864 ( ntsc / pal ) pixels sav eav 720 pixels 7.16.2 dvalid and timing signal interface for connection with devices having no itu-r.bt. 656 interface, the ak8853 dvalid signal output identifies the active video interval by remaining lo w throughout that period, as shown in the following figure. in fixed-clock mode, the internal clock is not sync hronized with the output si gnal, but a space of 122/132 (ntsc/pal) pixels is guaranteed betw een the horizontal sync signal and the start of the active video interval. video signal hsync dvalid clk27mout cb0 cr0 y0 y1 cb1 y2 cr1 y3 y719 cr359 y718 d[7:0] active video start position : t? ???? 122/132 pixels
[AK8853XQ/ vn] rev-e-00 30 2008/01 the ak8853 outputs the following signals from the hd, vd_f, and dvalid_f pins, and the indicated vd_f and dvalid_f output signals can also be se lected via the register settings shown below. timing signal output pin 525-line 625-line hd low for 4.7 s at 15.734 khz interval low for 4.7 s at 15.625 khz interval vd_f dvalid_f vd low during lines 4~6 and 266.5~269.5 low during lines 1~3.5 and 313.5~315 field odd-field: low; even-field: high dvalid active-low vfdsel[1:0]-bits: settings fo r vd/field/dvalid selection pin output vfdsel[1:0]-bits vd_f pin dvalid_f pin [00] vd signal dvalid signal [01] vd signal field signal [10] field signal dvalid signal [11] reserved reserved output timing with 525-line input even odd 523 524 525 1 2 3 4 5 6789 10 11 vd field hd cvbs even odd 264 265 266 267 268 269 270 271 263 262 272 273 274 261 field vd ? cvbs hd ? output timing with 625-line input hd vd field even odd cvbs 620 621 622 623 624 625 1 23456 8 7 hd vd even odd field cvbs 311 312 313 314 315 316 317 318 310 309 319 321 308 320 the output signal polarities of t he dtclk, hd, vd_f and dvalid_f pins can be reversed via ?output control register? and ?control 0 register? settings.
[AK8853XQ/ vn] rev-e-00 31 2008/01 7.17 automatic setup processing in auto detection mode, the ak8853 c an perform automatic setup proc essing in accordance with the detected signal. the automatic setup selection is made via the stu patoff-bit register, as shown in the table below. setup processing of the signal to be decoded consists of the following. luminance signal: y=(y-7.5)/0.925 color signal: u=u/0.925, v=v/0.925 automatic setup processing (ak8853 in auto detection mode) register setting detected signal setup-bit stupatoff-bit (automatic setup processing) detected signal setup processing status [0] disabled [0] [1] disabled [0] enabled ntsc-m, j pal-b, d, g, h, i, n pal-nc, 60 secam [1] [1] enabled [0] enabled [0] [1] disabled [0] enabled pal-m ntsc-4.43 [1] [1] enabled in the auto detection mode, the set up processing status will be determi ned by the register setting on the basis of the detected signal cat egory, with no detection as to the presence or absence of input signal setup. 7.18 pga (programmable gain amp) the pga, located in the input st age of the ak8853, can be set in a gai n range of -6~6 db in gain steps of 0.1 db. pga[7:0]-bits: sets the pga value. this register can read the agc setting value. if agc is enabled, the pga[7:0]-bits setting val ue has no effect, and the pga setting can be manually entered in the register only if agc is disabled. signal input to the ak8853 should be made with the input level attenua ted approximately 39% (-8.19 db) by resistance splitting.
[AK8853XQ/ vn] rev-e-00 32 2008/01 7.19 sync separation, sync detection, and black-level fine tuning the ak8853 performs sync separation and sync detec tion on the digitized i nput signal, uses the detected sync signal as the timi ng reference for the decoding proce ss, and calculates the phase error from the separated sync signal and applies it to control of the sampling clock. black-level tuning can be performed in the sync separ ation block. the black-level fine-tuning band, which is 10 bits wide before rec 601 conversion, c an be adjusted -8~+7 lsb in 1-lsb steps, with one step resulting in a change of about 0.4 lsb in the output code. bklvl[3:0]-bits: settings for black-level fine tuning bklvl[3:0]-bits code adjustment of black level approx. change in 601 level (lsb) [0001] +1 +0.4 [0010] +2 +0.8 [0011] +3 +1.2 [0100] +4 +1.6 [0101] +5 +2.0 [0110] +6 +2.4 [0111] +7 +2.8 [0000] default none [1000] ? 8 ? 3.2 [1001] ? 7 ? 2.8 [1010] ? 6 ? 2.4 [1011] ? 5 ? 2.0 [1100] ? 4 ? 1.6 [1101] ? 3 ? 1.2 [1110] ? 2 ? 0.8 [1111] ? 1 ? 0.4 the black level is adjusted upward or downward by the value of the setting, which must be in 2?s-complement form. black-level adjustment is al so enabled during the vertical blanking interval. 7.20 digital pedestal clamp the digitally converted input signal is clamped in the digital signal proc essing block. the internal clamp position depends on the input signal type (either 286 mv sync or 300 mv sync), but pedestal position is output as code 16 for both types. the digital pedestal clamp function c an adjust the time constant and set the coring level. dpct[1:0]-bits: settings for digita l pedestal clamp time constant dpct[1:0]-bits transition time constant notes [00] fast ? [01] middle ? [10] slow ? [11] disable digital pedestal clamp off dpcc[1:0]-bits: settings for di gital clamp pedestal coring level dpcc[1:0]-bits transition time constant (bit) notes [00] 1 ? [01] 2 ? [10] 3 ? [11] non-coring ?
[AK8853XQ/ vn] rev-e-00 33 2008/01 7.21 color killer the chroma signal quality of the i nput signal is determined by comparis on of its color burst level against the threshold setting in the color killer control register. if the level is bel ow the threshold, the color killer is activated, resulting in proce ssing of the input as a monochrome si gnal and thus with cbcr data fixed at 0x80. depending on the register setting, the color killer may also be activated by failure of the color decode pll lock. colkill-bit: settings for color killer on and off colkill-bit notes [0] enable ? [1] disable ? cklvl[3:0]-bits: for threshold setting; default setting [1000] = ? 23db. ckscm[1:0]-bits: used for threshold setting with secam input; expands 2-bit for cklvl[3:0]-bit ckilsel: settings for color killer activation ckilsel-bit condition for activation notes [0] burst level below threshold setting in cklvl[3:0]-bits ? [1] burst level below threshold se tting in cklvl[3:0]-bits, or failure of color decode pll lock ? 7.22 image quality adjustments image quality adjustments consist of contrast, brightness, sharpne ss, color saturation, and hue adjustment. all image quality adjustm ents are disabled during the vertical blanking interval, but contrast and brightness adjustment can be enabled by the register setting. 7.22.1 contrast adjustment cont[7:0]-bits: for contrast adjustm ent; default value 0x80 (no adjustment) contrast adjustment involves mult iplication by the gain factor setti ng in this register. the equation of the multiplication can be modifi ed by register setting as follows. if contsel = [0], then yout = (cont/128) x (yin ? 128) + 128 if contsel = [1], then yout = (cont/128) x yin yout: contrast obtained by the calculation yin: contrast befor e the calculation cont: contrast gain factor (register setting value) the gain factor can be set in the range 0~255. if the calculated value is outside the specified contrast range, it is clipped to t he upper ?254? or lower ?1? limit. wi th a control bit 601limit setting of [1], the output will be in the range 16~235. contsel-bit: settings for cont rast adjustment inclination contsel -bit inclination notes [0] toward luminance of 128 ? [1] toward luminance of 0 ?
[AK8853XQ/ vn] rev-e-00 34 2008/01 7.22.2 brightness adjustment br[7:0]-bits: for brightness adjustm ent; settings in 2?s complement; default value 0x00 (no adjustment) brightness adjustment involves multiplication of the 8bit data luminance signal, after itu-r bt.601 conversion, by the gain factor setti ng in this register, as follows. yout = yin + br yout: brightness obtained by the calculation yin: brightness before the calculation br: brightness gain factor (register setting value) the gain factor can be set in the range -127 to +127 in steps of 1, by 2?s complement entry. if the calculated value is outside t he specified contrast range, it is clipped to the upper ?254? or lower ?1? limit. with a control bit 601limit setting of [1], the output will be in the range 16~235. 7.22.3 color saturation adjustment sat[7:0]-bits: for color saturation adjust ment; default value 0x80 (no adjustment) saturation adjustment involves mult iplication of the color signal by the gain factor setting in this register. the calculated result is u/v demodulated. the gain factor can be set in the r ange 0 to 255/128, in steps of 1/128. 7.22.4 hue adjustment hue[7:0]-bits: for hue adjustment; settings in 2?s complement; default value 0x00 (no adjustment) the ak8853 can perform hue rotation with a phas e rotation range of 45 in steps of about 0.35. 7.22.5 sharpness adjustment sharpness adjustment is performed on the luminance signal as shown in the following process diagram. the filter characteristics and the coring level can be selected by fo llowing register. a sharp image can be obtained by selection of the filter wi th the appropriate characteristics. filter coring delay luminance signal before processing sharp[1:0]-bits shcore[1:0]-bits luminance signal after processing sharp[1:0]-bits: settings for fi lter characteristics selection sharp[1:0]-bits filter characteristics notes [00] no filtering filter disabled [01] min ? [10] middle ? [11] max ? shcore[1:0]-bits: settings for cori ng level after sharpness filtering shcore[1:0]-bits corin g level ( lsb ) notes [00] no coring [01] 1 [10] 2 [11] 3 settings apply only to filtered signal.
[AK8853XQ/ vn] rev-e-00 35 2008/01 vbiimgctl-bit: settings for brightness and cont rast adjustment status (on/off) during vbi vbiimgctl -bit status during vbi notes [0] disabled ? [1] enabled ? 7.23 luminance bandwidth adjustment luminance bandwidth adjustment can be performed fo r mpeg compression etc. the band-limiting filters for pre-compression limiting can be selected by the follo wing register settings. wi thout these filters, the frequency response of the luminance signal is determined by the decimation filter. lumfil[1:0]-bits: settings fo r luminance bandwidth filter lumfil[1:0]-bits filter characteristic notes [00] no filter -3 db at 6.29 mhz [01] narrow -3db at 2.94mhz [10] mid -3db at 3.30mhz [11] wide -3db at 4.00mhz 7.24 sepia output sepia-colored output of the decoded signal can be obtained by t he following register setting. sepia-bit: settings for sepi a output of decoded signal sepia ?bit out p ut notes [0] normal ? [1] sepia ? 7.25 vbi information decoding the ak8853 decodes closed-c aption, closed-caption- extended, vbid(cgms), and wss signals on the vertical blanking signal, and writes the decoded data into a storage register. the ak8853 reads each data bit in request vbi information register(r/w)- [3:0] as a decoding request and thereupon enters a data wait state. data detecti on and decoding to the storage regi ster are then performed which indicates the presence or absence of data at status 2 r egister-[3:0] for host. the host can therefore determine the stored values by readi ng the respective storage register s. the value in each storage register is retained until a new value is written in by data renewal. for vbid data (cgms-a), the crcc code is decoded and only the arithmetic result is stored in the register. signal type superimposed line line closed caption line21 (ntsc-m, j, ntsc-4.43, pal-m, 60) 525 closed caption extended data line284 (n tsc-m, j, ntsc-4.43, pal-m, 60) 525 vbid line20 / 283 (ntsc-m, j, ntsc-4.43, pal-m, 60) line20 / 333 (pal-b, d, g, h, i, n, nc, secam) 525 625 wss line23 (pal-b, d, g, h, i, n, nc, secam) 625 the storage registers for each of the signal types are as follows. for storage bit allocations, please refer to the respective register setting descriptions. closed caption 1 register, closed caption 2 register wss 1 register, wss 2 register extended data 1 register, extended data 2 register vbid 1 register, vbid 2 register
[AK8853XQ/ vn] rev-e-00 36 2008/01 7.26 internal status indicators the ak8853 shows the internal status, with the following bit allocation. nosig-bit: indicates pres ence or absence of signal nosig ?bit status of signal input notes [0] signal detected ? [1] no signal detected ? vlock-bit: indicates status of vlock vlock-bit status of synchronization notes [0] synchronized ? [1] non-synchronized ? colkilon: indicates status of color killer colkilon ?bit status of color killer notes [0] operation ? [1] not-operation ? sclkmode-bits: indicate s status of clock mode sclkmode ?bits clock mode notes [00] fixed-clock ? [01] line-locked ? [10] frame-locked ? [11] reserved ? pkwhite: indicates status of luminance dec ode result after passage through agc block pkwhite ?bit status of luminance decode result notes [0] normal ? [1] overflow ? ovcol: indicates status of color dec ode result after passage through acc block ovcol ?bit status of color decode result notes [0] normal ? [1] overflow ? status 2-ragister: indicates clos ed caption, extended data, vbid, and wss signal status, with decoding field status shown in realfld-bit and adaptive agc status in agcsts-bit. realfld -bit decoding field notes [0] even ? [1] odd ? agcsts -bit status of agc operation notes [0] sync agc operation ? [1] peak agc operation ?
[AK8853XQ/ vn] rev-e-00 37 2008/01 macrovision status-register: indi cates macrovision signal type, if decoded data contains macrovision signal bit register name description definition bit 0 agcdet agc process detect [0]: no macrovision agc process detected [1]: macrovision agc process detected bit 1 csdet color stripe detect [0]: no macrovision color stripe process detected [1]: macrovision color stripe process detected bit 2 cstype color stripe type [0]: color stripe type 2 in input signal [1]: color stripe type 3 in input signal input video status-register: indicates status of autom atic input signal detection bit register name status indication bit 0 ~ bit 1 st_vscf0 ~ st_vscf1 status of video sub-carrier frequency input signal subc arrier frequency: [st_vscf1: st_vscf0] (mhz) [00]: 3.57954545 (ntsc-m, j) [01]: 3.57561149 (pal-m) [10]: 3.58205625 (pal-nc) [11]: 4.43361875 (pal-b, d, g, h, i, n, 60; ntsc-4.43, secam*) bit 2 ~ bit 3 st_vcen0 ~ st_vcen1 status of video color encode input signal color encode format: [st_vcen1: st_vcen0] [00]: ntsc [01]: pal [10]: secam [11]: reserved bit 4 st_vlf status of video line frequency input signal line frequency [0]: 525 line (ntsc-m, j; ntsc-4.43, pal-m, 60) [1]: 625 line (pal-b, d, g, h, i, n, nc; secam) bit 5 st_bw status of b/w signal input signal monochrome or non-monochrome 1 : [0]: non-monochrome detected [1]: monochrome bit 6 undef un_define bit input signal pres ence or absence 2 : [0]: input signal detected [1]: no input signal detected bit 7 fixed input video standard fixed bit input signal detection phase 3 : [0]: input signal search in progress [1]: input signal search complete *if input signal is identified as sec am, st_vscf[1:0] changes to [11]. 1 monochrome auto detection is enabl ed if the color killer setting is on(colkill-bit = [1]). st_bw-bit changes to [1] when the color killer operates. if the user has deliberately entered the b/w-bi t setting sub address 0x01, input signal detection is limited to 525/625 line detection, and only the st_vlf information is relevant. 2 shows results of input signal detection. if an input signal is detected, t he value is [0]; if no input signal is detected, the value is [1]. 3 shows the operating phase of the automatic input signal detector. the value is [0] while the detection operation is in progress, and [1] when it is completed; thus, when undef-bit = [1], fixed-bit = [0].
[AK8853XQ/ vn] rev-e-00 38 2008/01 the vbi information storage registers are as follows. closed caption 1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 closed caption 2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cc15 cc14 cc13 cc12 cc11 cc10 cc9 cc8 wss 1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 g2-7 g2-6 g2-5 g2-4 g1-3 g1-2 g1-1 g1-0 wss 2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved g4-13 g4-12 g4-11 g3-10 g3-9 g3-8 extended data 1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext7 ext6 ext5 ext4 ext3 ext2 ext1 ext0 extended data 2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext15 ext14 ext13 ext12 ext11 ext10 ext9 ext8 vbid 1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved vbid1 vbid2 vbid3 vbid4 vbid5 vbid6 vbid 2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbid7 vbid8 vbid9 vbid10 vbid11 vbid12 vbid13 vbid14
[AK8853XQ/ vn] rev-e-00 39 2008/01 8. device control interface the ak8853 is controlled via i 2 c bus control interface, as described below. 8.1 i 2 c bus slave address the i 2 c slave address can be selected by a sela pi n setting of either [1000100] or [1000101]. slave address sela pin status msb lsb pulldown [low] 1 0 0 0 1 0 0 r/w pullup [high] 1 0 0 0 1 0 1 r/w 8.2 i 2 c control sequence 8.2.1 write sequence after receiving a write-mode slave address first by te, the ak8853 receives the sub-address in the second byte and data in the subseque nt bytes. the write sequence may be single-byte or multi-byte. single-byte write sequence s slave address w a sub address a data a stp 8-bits 1- bit 8-bits 1- bit 8-bits 1- bit multi-byte write sequence (m-byt es, sequential write operation) s slave address w a sub address (n) a data(n) a data (n+1) a data (n+m) a stp 8-bits 1- bit 8-bits 1- bit 8-bits 1- bit 8-bits 1- bit ??????? 8-bits 1- bit 8.2.2 read sequence after receiving a read-mode salve address as the first byte, the ak8853 sends data in the second and subsequent bytes. s slave addres s w a sub address (n) a rs slave address r a data1 a data 2 a data3 a ????? 8-bits 1 8-bits 1 8-bits 1 8-bits 1 8-bits 1 8-bits 1 ????????? ??? data n !a stp 8-bits 1 symbols and abbreviations s: start condition rs: repeated start condition a: acknowledge (sda low) !a: not acknowledge (sda high) stp: stop condition r/w: 1: read; 0: write : received from master devi ce (normally microprocessor) : output by slave device (ak8853)
[AK8853XQ/ vn] rev-e-00 40 2008/01 9. register definitions sub address register default r/w function 0x00 afe control register 0x00 r/w analog front-end setting 0x01 input video standard register 0x00 r/w input video signal format setting 0x02 output format regsiter 0x00 r/w output data format setting 0x03 ndmode register 0x00 r/w auto detection limit setting 0x04 output control register 0x00 r/w output pin status setting 0x05 start and delay control register 0x00 r/w output data setting 0x06 agc & acc control register 0x00 r/w agc and acc setting 0x07 control 0 register 0x00 r/w control register type 0x08 control 1 register 0x00 r/w control register type 0x09 control 2 register 0x00 r/w control register type 0x0a pga control register 0x3e r/w pga gain setting 0x0b reserved register 0x00 r/w reserved 0x0c pedestal level cont rol register 0x00 r/w pedestal level adjustment 0x0d color killer control register 0x08 r/w color killer setting 0x0e contrast control register 0x80 r/w contrast adjustment 0x0f brightness control register 0x00 r/w brightness adjustment 0x10 image control register 0x00 r/w image control setting 0x11 saturation control register 0x80 r/w saturation adjustment 0x12 hue control register 0x00 r/w hue adjustment 0x13 high slice data set register 0xeb r/w vbi slicer data high setting 0x14 low slice data set register 0x10 r/w vbi slicer data low setting 0x15 request vbi infomation register 0x00 r/w vbi interval decode request setting 0x16 status 1 register r internal status indicator 0x17 status 2 register r internal status indicator 0x18 macrovision status register r input macrovision signal indicator 0x19 input video stat us register r input signal detection indicator 0x1a closed caption 1 register r closed caption data indicator 0x1b closed caption 2 register r closed caption data indication 0x1c wss 1 register r wss data indicator 0x1d wss 2 register r wss data indicator 0x1e extended data 1 register r closed caption extended data indicator 0x1f extended data 2 register r closed caption extended data indicator 0x20 vbid 1 register r vbid data indicator 0x21 vbid 2 register r vbid data indicator 0x22 device and revision id register r device id and revision id indicator
[AK8853XQ/ vn] rev-e-00 41 2008/01 sub address register default r/w function 0x23 reserved r reserved register 0x24 reserved 0x08 r/w reserved register 0x25 reserved 0x01 r/w reserved register 0x26 reserved 0x00 r/w reserved register 0x27 reserved 0x00 r/w reserved register 0x28 reserved 0x00 r/w reserved register 0x29 reserved 0x00 r/w reserved register 0x2a reserved 0x3a r/w reserved register 0x2b reserved 0x00 r/w reserved register 0x2c reserved 0x00 r/w reserved register 0x2d reserved 0x00 r/w reserved register 0x2e reserved 0x00 r/w reserved register 0x2f reserved 0x84 r/w reserved register 0x30 reserved 0x7c r/w reserved register 0x31 reserved 0x3c r/w reserved register 0x32 reserved 0x0a r/w reserved register 0x33 reserved 0x00 r/w reserved register 0x34 reserved 0x00 r/w reserved register 0x35 reserved 0x40 r/w reserved register 0x36 reserved 0x5d r/w reserved register 0x37 reserved 0xa9 r/w reserved register 0x38 reserved 0x7b r/w reserved register 0x39 reserved 0xdd r/w reserved register 0x3a reserved 0x00 r/w reserved register 0x3b reserved 0x00 r/w reserved register 0x3c reserved 0x08 r/w reserved register 0x3d reserved 0x08 r/w reserved register 0x3e reserved 0x00 r/w reserved register 0x3f reserved 0x00 r/w reserved register for all other registers, write-in is prohibited. for all reserved registers, write-in must be limited to the default value.
[AK8853XQ/ vn] rev-e-00 42 2008/01 10. register settings overview afe control register (r/w) [sub address 0x00], for input signal selection sub address 0x00 default value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved insel1 insel0 default value 0 0 0 0 0 0 0 0 afe control register definition bit register name r / w definition bit 0 ~ bit 1 insel0 ~ insel1 input select r / w input video signal selection: [00]: ain1 (cvbs) [01]: ain2 (cvbs) [10]: ain3 (cvbs) [11]: ain4 (cvbs) bit 2 ~ bit 7 reserved reserved r / w reserved
[AK8853XQ/ vn] rev-e-00 43 2008/01 input video standard register (r/w) [sub address 0x01], for input signal selection sub address 0x01 default value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 autodet setup bw vlf vcen1 vcen0 vscf1 vscf0 default value 0 0 0 0 0 0 0 0 input video standard register definition bit register name r/w definition bit 0 ~ bit 1 vscf0 ~ vscf1 video sub-carrier frequency r/w input video signal subcarrier frequency setting [vscf1: vscf0] (mhz) [00]: 3.57954545 (ntsc-m,j) [01]: 3.57561149 (pal-m) [10]: 3.58205625 (pal-nc) [11]: 4.43361875 (pal-b,d,g,h,i,n,60 , ntsc-4.43 , secam*) bit 2 ~ bit 3 vcen0 ~ vcen1 video color encode r/w input signal color ecode format setting [vcen1: vcen0] [00]: ntsc [01]: pal [10]: secam [11]: reserved bit 4 vlf video line frequency r/w input signal line frequency setting [0]: 525line (ntsc-m,j , ntsc-4.43 , pal-m,60) [1]: 625 line (pal-b, d, g, h, i, n, pal-nc, secam) bit 5 bw black & white r/w monochrome mode (on/off) setting [0]: monochrome mode off [1]: monochrome mode on bit 6 setup setup r/w setup process setting [0]: process as input signal with no setup [1]: process as input signal with setup bit 7 autodet video standard auto detect r/w input signal auto detection setting [0]: off (auto detection disabled; set manually) [1]: on (auto detection enabled) *for secam input signal, change vscf[1:0] setting to [11].
[AK8853XQ/ vn] rev-e-00 44 2008/01 output format register (r/w) [sub address 0x02], for output data format setting sub address 0x02 default value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbidec1 vbidec0 sllvl trsvsel 601limit vbil2 vbil1 vbil0 default value 0 0 0 0 0 0 0 0 output format register definition bit register name r/w definition bit 0 ~ bit 2 vbil0 ~ vbil2 vertical blanking length r/w vertical blanking interval length setting, entered as difference from the default settings the default settings are: 525-line: lines1~ 19 and 263.5~282.5 625-line: lines 623.5~22 and 311~335.5 examples of lengthening and shortening: if lengthened 1 line, the interval becomes 525-line: lines1~20 and 263.5~283.5 625-line: lines 623.5~23 and 311~336.5 if shortened 1 line, the interval becomes 525-line: lines1~18 and 263.5~281.5 625-line: lines 623.5~21 and 311~334.5 [vbil2: vbil0] [001]: vbi lengthened 1 line [010]: vbi lengthened 2 lines [011]: vbi lengthened 3 lines [000]: default [101]: vbi shortened 3 lines [110]: vbi shortened 2 lines [111]: vbi shortened 1 line [100]: reserved bit 3 601limit 601 output limit r/w output data code lim it (min-max) setting [0]: 1-254 (y/cb/cr) [1]: 16-235 (y) /16-240 (cb/cr) bit 4 trsvsel time reference signal v select bit r/w setting of lines for ?time reference signal? v-bit value change in itu-r bt.656 format with 525-line input setting [0]: v=1 (lines 1~9 and 264~272) v=0 (lines 10~263 and 273~525) setting [1]: v=1 (lines 1~19 and 264~282) v=0 (lines 20~263 and 283~525) with 625-line input always (regardless of setting in this register): v=1 (lines 1~22 and 311~335) v=0 (lines 23~310 and 336~623) bit 5 sllvl slice level r/w slice level setting [0]: slice level approx. 25 ire [1]: slice level approx. 50 ire bit 6 ~ bit 7 vbidec0 ~ vbidec1 vbi decode r/w setting for type of data output during interval set in vertical blanking interval register [ vbidec1: vbidec0 ] [00]: black level data output [01]: monochrome data output [10]: slice result data output [11]: reserved
[AK8853XQ/ vn] rev-e-00 45 2008/01 ndmode register (r/w) [sub address 0x03], for lim iting auto input video si gnal detection candidates sub address 0x03 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nd625l nd525l ndpal60 ndntsc443 reserved ndsecam ndpalnc ndpalm default value 0 0 0 0 0 0 0 0 ndmode register definition bit register name r/w definition bit 0 ndpalm no detect pal-m bit r/w [0]: pal-m candidate [1]: pal-m non-candidate bit 1 ndpalnc no detect pal-nc bit r/w [0]: pal-nc candidate [1]: pal-nc non-candidate bit 2 ndsecam no detect secam bit r/w [0]: secam candidate [1]: secam non-candidate bit 3 reserved reserved r/w reserved bit 4 ndntsc443 no detect ntsc-4.43 bit r/w [0]: ntsc-4.43 candidate [1]: ntsc-4.43 non-candidate bit 5 ndpal60 no detect pal-60 bit r/w [0]: pal-60 candidate [1]: pal-60 non-candidate bit 6 nd525l no detect 525line bit r/w [0]: 525 line candidate [1]: 525 line non-candidate bit 7 nd625l no detect 625line bit r/w [0]: 625 line candidate [1]: 625 line non-candidate in making the above register settings, the following restrictions apply, 1. setting both ndntsc443(bit 4) and ndpal 60(bit 5) to [1] (high) is prohibited. 2. setting both nd525l(bit 6) and nd625l(bit 7) to [1] (high) is prohibited. 3. to limit candidate formats, it is necessary to have the auto detection mode off while first setting the register to non-limited signal status and next the ndmode settings, and then setting the auto detection mode to on.
[AK8853XQ/ vn] rev-e-00 46 2008/01 output control register (r/w) [sub address 0x04], for output pin output status setting sub address 0x04 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clkinv dvalid_fsel vd_fsel hl nl dvalid_fl vd_fl dl default value 0 0 0 0 0 0 0 0 output control register definition bit register name r/w definition bit 0 dl d output low bit r/w [0]: normal output [1]: [d7: d0] pin output fixed at low bit 1 vd_fl vd/field low bit r/w [0]: normal output [1]: vd_f pin output fixed at low bit 2 dvalid_fl dvalid/field low bit r/w [0]: normal output [1]: dvalid_f pin output fixed at low bit 3 nl nsig low bit r/w [0]: normal output [1]: nsig pin output fixed at low bit 4 hl hd low bit r/w [0]: normal output [1]: hd pin output fixed at low bit 5 vd_fsel vd/field select bit r/w vd_f pin output signal selection [0]: vd signal output [1]: field signal output bit 6 dvalid_fsel dvalid/field select bit r/w dvalid_f pin output signal selection [0]: dvalid signal output [1]: field signal output bit 7 clkinv clk invert set bit r/w dtclk signal output polarity selection [0]: normal output (write in data at rising edge) [1]: data and clock reversed (write in data at falling edge) note: output control via pins oe, pdn, and rstn takes priority, regardless of the above settings.
[AK8853XQ/ vn] rev-e-00 47 2008/01 start and delay control register (r/w) [sub address 0x05], for data output setting sub address 0x05 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved actsta2 actsta1 actsta0 reserved reserved reserved reserved default value 0 0 0 0 0 0 0 0 start and delay control register definition bit register name r/w definition bit 0 ~ bit 3 reserved reserved r/w reserved bit 4 ~ bit 6 actsta0 ~ actsta2 active video start control bit r/w fine-tuning video data decode start position by delay or advance in 1-sample units 1 sample clock (13.5 mhz; approx. 74 ns) [actsta2: actsta0] [001]: 1-sample delay [010]: 2-sample delay [011]: 3-sample delay [000]: normal start position [101]: 3-sample advance [110]: 2-sample advance [111]: 1-sample advance [100]: reserved bit 7 reserved reserved r/w reserved
[AK8853XQ/ vn] rev-e-00 48 2008/01 agc & acc control register (r/w) [s ub address 0x06], for agc and acc setting sub address 0x06 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 accfrz acc1 acc0 agcfrz agcc1 agcc0 agct1 agct0 default value 0 0 0 0 0 0 0 0 agc control register definition bit register name r/w definition bit 0 ~ bit 1 agct0 ~ agct1 agc time constant r/w agc time constant (t) setting (if disabled, pga can be set manually) [agct1: agct0] [00]: disable [01]: fast [t = 1 field] [10]: middle [t = 7 fields] [11]: slow [t = 29 fields ] bit 2 ~ bit 3 agcc0 ~ agcc1 agc coring control r/w agc non-sensing bandwidth (lsb) setting [agcc1: agcc0] [00]: 2 lsb [01]: 3 lsb [10]: 4 lsb [11]: no non-sensing band bit 4 agcfrz agc freeze r/w agc freeze function (on/off) setting (agc set values are saved during freeze) [0]: non-frozen [1]: frozen bit 5 ~ bit 6 acc0 ~ acc1 acc time constant r/w acc time constant (t) setting [acct1: acct0] [00]: disable [01]: fast [t = 2fields] [10]: middle [t =8fields] [11]: slow [t = 30fields] bit 7 accfrz acc freeze r/w acc freeze function (on/off) setting (acc set values are saved during freeze) [0] : non-frozen [1] : frozen
[AK8853XQ/ vn] rev-e-00 49 2008/01 control 0 register (r/w) [sub address 0x07], for the following function setting sub address 0x07 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dvalid_fp vd_fp hdp c443fil0 c443fil0 c358fil1 c358fil0 agctl default value 0 0 0 0 0 0 0 0 control 0 register definition bit register name r/w definition bit 0 agctl agc transition level r/w transition speed setti ng, between peak agc and sync agc [0]: quick [1]: slow bit 1 ~ bit 2 c358fil0 ~ c358fil1 c filter_358 select bit r/w c-filter bandwidth setting, for 3.58 mhz subcarrier system signal [c358fil1: c358fil0] [00]: 3.58 narrow [01]: 3.58 medium [10]: 3.58 wide [11]: reserved bit 3 ~ bit 4 c443fil0 ~ c443fil1 c filter_443 select bit r/w c-filter bandwidth setting, for 4.43 mhz subcarrier system signal [c443fil1: c443fil0] [00]: 4.43 narrow [01]: 4.43 medium [10]: 4.43 wide [11]: reserved bit 5 hdp hd pin polarity set bit r/w hd signal polarity setting [0]: active low [1]: active high bit 6 vd_fp vd_f pin polarity set bit r/w vd_f pin output polarity setting if in vd signal output mode [0]: active low [1]: active high if in field signal output mode [0]: odd-field low, even-field high [1]: even-field low, odd-field high bit 7 dvalid_fp dvalid_f pin polarity set bit r/w dvalid_f pin output signal polarity setting if in dvalid signal output mode [0]: active low [1]: active high if in field signal output mode [0]: odd-field low, even-field high [1]: even-field low, odd-field high
[AK8853XQ/ vn] rev-e-00 50 2008/01 control 1 register (r/w) [sub address 0x08], for the following function setting sub address 0x08 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clkmode1 clkmode0 intpol1 intpol0 reserved uvfilsel ycsep1 ycsep0 default value 0 0 0 0 0 0 0 0 control 1 register definition bit register name r/w definition bit 0 ~ bit 1 ycsep0 ~ ycsep1 yc separation control r/w y/c separation setting [ycsep1: ycsep0] [00]: adaptive y/c separation [01]: 1-dimensional y/c separation [10]: 2-dimensional y/c separation [11]: reserved bit 2 uvfilsel uv filter select r/w uv filter bandwidth setting [0]: wide [1]: narrow bit 3 reserved reserved r/w reserved bit 4 ~ bit 5 intpol0 ~ intpol1 interpolator mode select r/w pixel interpolator setting [intpol1: intpol0] [00]: auto [01]: on [10]: off [11]: reserved bit 6 ~ bit 7 clkmode0 ~ clkmode1 clock mode select r/w clock mode setting [clkmode1: clkmode0] [00]: automatic transition mode [01]: line-locked clock mode [10]: frame-locked clock mode [11]: fixed-clock mode
[AK8853XQ/ vn] rev-e-00 51 2008/01 control 2 register (r/w) [sub address 0x09], for the following function setting sub address 0x09 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ckilsel stupatoff errhnd1 errhnd0 nsigmd1 nsigmd0 dpal1 dpal0 default value 0 0 0 0 0 0 0 0 control 2 register definition bit register name r/w definition bit 0 ~ bit 1 dpal0 ~ dpal1 deluxe pal r/w setting for color averaging (pal phase correction block) also applicable to ntsc. [dpal1: dpal0] [00]: adaptive phase correction on [01]: phase correction on [10]: phase correction off [11]: reserved bit 2 ~ bit 3 nsigmd0 ~ nsigmd1 no signal output mode r/w setting for output on no-signal detection [nsigmd1: nsigmd0] [00]: black-level output [01]: blue-level (blueback) output [10]: input status (sandstorm) output [11]: reserved bit 4 ~ bit 5 errhnd0 ~ errhnd1 656 error handling r/w setting for processing if itu-r bt.656 output is not possible [errhnd1: errhnd0] [00]: line drop or repeat [01]: pixel drop or repeat, in final line of field [10]: line drop or repeat, in final line of frame [11]: reserved bit 6 stupatoff setup auto control off r/w setup auto switching setting (on/off) in auto signal detection mode [0]: auto setup switching on [1]: auto setup switching off bit 7 ckilsel color killer select r/w color killer activation setting [0]: activation when burst color level is below cklvl[3:0]-bits threshold setting [1]: activation when burst color level is below cklvl[3:0]-bits threshold setting or color decode pll lock fails
[AK8853XQ/ vn] rev-e-00 52 2008/01 pga control register (r/w) [sub address 0x0a], for pga gain setting sub address 0x0a default value: 0x3e bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved pga_6 pga_5 pga_4 pga_3 pga_2 pga_1 pga_0 default value 0 0 1 1 1 1 1 0 pga control register definition bit register name r/w definition bit 0 ~ bit 6 pga_0 ~ pga_6 pga gain set r/w pga gain setting, in steps of approx. 0.1 db bit 7 reserved reserved r/w reserved reserved register (r/w) [sub address 0x0b] sub address 0x0b default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved rese rved reserved reserved reserved default value 0 0 0 0 0 0 0 0
[AK8853XQ/ vn] rev-e-00 53 2008/01 pedestal level control register (r/w) [sub addr ess 0x0c], for pedestal level adjustment setting sub address 0x0c default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dpcc1 dpcc0 dpct1 dpct0 bklvl3 bklvl2 bklvl1 bklvl0 default value 0 0 0 0 0 0 0 0 pedestal level control register definition bit register name r/w definition bit 0 ~ bit 3 bklvl0 ~ bklvl3 black level r/w setting for change from current pedestal level by adding to or subtracting from black level [bklvl3: bklvl0] [0001]: add 1 [0010]: add 2 [0011]: add 3 [0100]: add 4 [0101]: add 5 [0110]: add 6 [0111]: add 7 [0000]: default [1000]: subtract 8 [1001]: subtract 7 [1010]: subtract 6 [1011]: subtract 5 [1100]: subtract 4 [1101]: subtract 3 [1110]: subtract 2 [1111]: subtract 1 bit 4 ~ bit 5 dpct0 ~ dpct1 digital pedestal clamp control r/w time-constant setting for digital pedestal clamp [dpct1: dpct0] [00]: fast [01]: middle [10]: slow [11]: disable bit 6 ~ bit 7 dpcc0 ~ dpcc1 digital pedestal clamp coring control r/w non-sensing bandwidth setting for digital pedestal clamp [dpcc1: dpcc0] [00]: 1bit [01]: 2bits [10]: 3bits [11]: no non-sensing band
[AK8853XQ/ vn] rev-e-00 54 2008/01 color killer control register (r/w) [sub address 0x0d], for color killer setting sub address 0x0d default value: 0x08 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 colkill contsel ckscm1 ckscm0 cklvl3 cklvl2 cklvl1 cklvl0 default value 0 0 0 0 1 0 0 0 color killer control register definition bit register name r/w definition bit 0 ~ bit 3 cklvl0 ~ cklvl3 color killer level control r/w burst level setting for color killer activation default value, approx. ? 23 db bit 4 ~ bit 5 ckscm0 ~ ckscm1 color killer level for secam r/w burst level setting for color killer activation in secam mode adds 2 bits to cklvl[3:0] bit 6 contsel contrast select bit r/w contrast selector [0]: toward luminance of 128 [1]: toward luminance of 0 bit 7 colkill colo r killer set r/w color killer on/off setting [0]: enable [1]: disable
[AK8853XQ/ vn] rev-e-00 55 2008/01 contrast control register (r/w) [sub address 0x0e], for contrast adjustment sub address 0x0e default value: 0x80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 default value 1 0 0 0 0 0 0 0 contrast control register definition bit register name r/w definition bit 0 ~ bit 7 cont0 ~ cont1 contrast control r/w register for contrast adjustment in steps of 1/128 in range 1~255/128 from default value of 0x80 brightness control register (r/w) [sub address 0x0f], for brightness adjustment sub address 0x0f default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 br7 br 6 br 5 br 4 br 3 br 2 br 1 br 0 default value 0 0 0 0 0 0 0 0 brightness control register definition bit register name r/w definition bit 0 ~ bit 7 br0 ~ br7 brightness control r/w register for brightness adjustment in steps of 1 by 8-bit code setting in 2?s complement
[AK8853XQ/ vn] rev-e-00 56 2008/01 image control register (r/w) [sub address 0x10] for adjustment image sub address 0x10 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbiimgctl sepia lumfil1 lumfil0 shcore1 shcore0 sharp1 sharp0 default value 0 0 0 0 0 0 0 0 image control register definition bit register name r/w definition bit 0 ~ bit 1 sharp0 ~ sharp1 sharpness control r/w sharpness control (filter effect) setting [sharp1: sharp0] [00]: no filtering [01]: min effect [10]: middle effect [11]: max effect bit 2 ~ bit 3 shcore0 ~ shcore1 sharpness coring r/w setting for level of coring after passage through sharpness filter enabled except with [sharp1:sharp0] register setting of [00] [shcore1: shcore0] [00]: no coring [01]: 1 lsb [10]: 2 lsb [11]: 3 lsb bit 4 ~ bit 5 lumfil0 ~ lumfil1 luminance filter r/w setting for luminance band limit filter [lumfil1: lumfil0] [00]: no filtering [01]: narrow [10]: mid [11]: wide bit 6 sepia sepia output r/w setting (on/off) for sepia coloring of decode results [0]: normal output [1]: sepia output bit 7 vbiimgctl vbi image control r/w setting (on/off) for image adjustment during brightness and contrast adjustment vbi [0]: image adjustment inactive during vbi [1]: image adjustment active during vbi
[AK8853XQ/ vn] rev-e-00 57 2008/01 saturation control register (r/w) [sub addr ess 0x11], for saturation level adjustment sub address 0x11 default value: 0x80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sat 7 sat 6 sat 5 sat 4 sat 3 sat 2 sat 1 sat 0 default value 1 0 0 0 0 0 0 0 saturation control register definition bit register name r/w definition bit 0 ~ bit 7 sat0 ~ sat7 saturation control r/w register for saturation level adjustment in steps of 1/128 in range 1~255/128 from default value of 0x80 hue control register (r/w) [sub address 0x12], for hue adjustment sub address 0x12 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hue 7 hue 6 hue 5 hue 4 hue 3 hue 2 hue 1 hue 0 default value 0 0 0 0 0 0 0 0 hue control register definition bit register name r/w definition bit 0 ~ bit 7 hue0 ~ hue7 hue control r/w register for hue adjustment in steps of 1/128 in range 45 in 2?s complement
[AK8853XQ/ vn] rev-e-00 58 2008/01 high slice data set register (r/w) [sub address 0x13], for vbi slicer sub address 0x13 default value: 0xeb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h7 h6 h5 h4 h3 h2 h1 h0 default value 1 1 1 0 1 0 1 1 high slice data set register definition bit register name r/w definition bit 0 ~ bit 7 h0 ~ h7 high data 0~7 set r/w register for setting sliced data from vbi slicer to high value (default code is 235) important: corresponds to 601 special code if set to 0x00 or 0xff low slice data set register (r/w) [sub address 0x14], for vbi slicer sub address 0x14 default value: 0x10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l7 l 6 l 5 l 4 l 3 l 2 l 1 l 0 default value 0 0 0 1 0 0 0 0 low slice data set r egister definition bit register name r/w definition bit 0 ~ bit 7 l0 ~ l7 low data 0~7 set r/w register for setting sliced data from vbi slicer to low value (default code is 16) important: corresponds to 601 special code if set to 0x00 or 0xff
[AK8853XQ/ vn] rev-e-00 59 2008/01 request vbi infomation register (r/w) [sub addr ess 0x15], for data decode during vbi interval sub address 0x15 default value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved wssrq vbidrq extrq ccrq default value 0 0 0 0 0 0 0 0 request vbi infomation register definition bit register name r/w definition bit 0 ccrq closed caption decode request r/w setting (on/off) for closed caption decode request [0]: no request (off) [1]: request (on) bit 1 extrq extended data decode request r/w setting (on/off) for extended data decode request [0]: no request (off) [1]: request (on) bit 2 vbidrq vbid decode request r/w setting (on/off) for vbid decode request [0]: no request (off) [1]: request (on) bit 3 wssrq wss decode request r/w setting (on/off) for wss decode request [0]: no request (off) [1]: request (on) bit 4 ~ bit 7 reserved reserved r/w reserved
[AK8853XQ/ vn] rev-e-00 60 2008/01 status 1 register (r) [sub address 0x16] for shows ak8853 internal status sub address 0x16 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ovcol pkwhite sclkmode1 sclkmode0 colkilon frmstd vlock nosig status 1 register definition bit register name r/w definition bit 0 nosig no signal r input signal indicator [0]: input signal present [1]: input signal absent bit 1 vlock video locked r input signal vlock synchronization status indicator [0]: input signal synchronized [1]: input signal non-synchronized bit 2 frmstd frame standard r input signal interlace status indicator [0]: input signal 525/625 interlaced [1]: input signal not 525/625 interlaced bit 3 colkilon color killer r color killer status indicator [0]: color killer not operation [1]: color killer operation bit 4 ~ bit 5 sclkmode0 ~ sclkmode1 clock mode r clock mode indicator [sclkmode1: sclkmode0] [00]: fixed-clock mode [01]: line-locked clock mode [10]: frame-locked clock mode [11]: reserved bit 6 pkwhite peak white detection r luminance decode result flow status indicator, after passage through agc block [0]: normal [1]: overflow bit 7 ovcol over color level r color decode result flow status indicator, after passage through acc block [0]: normal [1]: overflow (excessive color signal input)
[AK8853XQ/ vn] rev-e-00 61 2008/01 status 2 register (r) [sub address 0x17] for shows ak8853 internal status sub address 0x17 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved agcsts reserved wssdet vbiddet extdet ccdet status 2 register definition bit register name r/w definition bit 0 ccdet closed caption detect r indicator for presence of decoded data in closed caption 1 2 register [0]: no closed caption data present [1]: closed caption data present bit 1 extdet extended data detect r indicator for presence of decoded data in extended data 1,2 register [0]: no extended data present [1]: extended data present bit 2 vbiddet vbid data detect r indicator for presence of decoded data in vbid 1,2 register [0]: no vbid data present [1]: vbid data present bit 3 wssdet wss data detect r indicator for presence of decoded data in wss 1,2 register [0]: no wss data present [1]: wss data present bit 4 realfld real field r input signal field status (even/odd) indicator [0]: even field [1]: odd field bit 5 agcsts agc status bit r [0]: sync agc active [1]: peak agc active bit 6 ~ bit 7 reserved reserved r reserved
[AK8853XQ/ vn] rev-e-00 62 2008/01 macrovision status register (r) [sub address 0x18] for macrovision status sub address 0x18 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved cstype csdet agcdet macrovision status register definition bit register name r/w definition bit 0 agcdet agc process detect r indicator for presence of macrovision agc in input signal [0]: no macrovision agc present [1]: macrovision agc present bit 1 csdet color stripe detect r indicator for presence of macrovision color stripe in input signal [0]: no color stripe present [1]: color stripe present bit 2 cstype color stripe type r indicator for type of color stripe included in input signal [0]: color stripe type 2 [1]: color stripe type 3 bit 3 ~ bit 7 reserved reserved r reserved
[AK8853XQ/ vn] rev-e-00 63 2008/01 input video status regist er (r) [sub address 0x19] for auto detection mode sub address 0x19 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fixed undef st_b/w st_vlf st_vcen1 st_vcen0 st_vscf1 st_vscf0 input video status register definition bit register name r/w definition bit 0 ~ bit 1 st_vscf0 ~ st_vscf1 status of video sub-carrier frequency r input video signal subcarrier frequency indicator [st_vscf1: st_vscf0] ( mhz ) [00]: 3.57954545 (ntsc-m,j) [01]: 3.57561149 (pal-m) [10]: 3.58205625 (pal-nc) [11]: 4.43361875 (pal-b,d,g,h,i,n,60 , ntsc-4.43 , secam*) bit 2 ~ bit 3 st_vcen0 ~ st_vcen1 status of video color encode r input signal color encode format indicator [st_vcen1: st_vcen0] [00]: ntsc [01]: pal [10]: secam [11]: reserved bit 4 st_vlf status of video line frequency r input signal line number indicator [0]: 525-line(ntsc-m,j , ntsc-4.43 , pal-m,60) [1]: 625-line (pal-b,d,g,h,i,n,nc , secam) bit 5 st_bw status of b/w signal r input signal monochrome indicator [0]: not monochrome [1]: monochrome bit 6 undef un_define bit r input signal detection indicator [0]: input signal detected [1]: input signal not detected bit 7 fixed input video standard fixed bit r input signal detection process status [0]: detection process in progress [1]: detection process completed *if secam input signal is detect ed, st_vscf[1:0] goes to [11].
[AK8853XQ/ vn] rev-e-00 64 2008/01 closed caption 1 register (r) [sub address 0x1a] closed caption data storage register sub address 0x1a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 closed caption 2 register (r) [sub address 0x1b] closed caption data storage register sub address 0x1b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cc15 cc14 cc13 cc12 cc11 cc10 cc9 cc8 wss 1 register (r) [sub address 0x1c] wss data storage register sub address 0x1c bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 g2-7 g2-6 g2-5 g2-4 g1-3 g1-2 g1-1 g1-0 wss 2 register (r) [sub address 0x1d] wss data storage register sub address 0x1d bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved g4-13 g4-12 g4-11 g3-10 g3-9 g3-8 extended data 1 register (r) [sub address 0x1e] closed caption extended data storage register sub address 0x1e bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext7 ext6 ext5 ext4 ext3 ext2 ext1 ext0 extended data 2 register (r) [sub address 0x1f] closed caption extended data storage register sub address 0x1f bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext15 ext14 ext13 ext12 ext11 ext10 ext9 ext8 vbid 1 register (r) [sub address 0x20] vbid data storage register sub address 0x20 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved vbid1 vbid2 vbid3 vbid4 vbid5 vbid6 vbid 2 register (r) [sub address 0x21] vbid data storage register sub address 0x21 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbid7 vbid8 vbid9 vbid10 vbid11 vbid12 vbid13 vbid14
[AK8853XQ/ vn] rev-e-00 65 2008/01 device and revision id register (r) [sub address 0x22] device id and revision indicator device id: [0x35] revision id: initially 0x00; revision number changes only when control software should be modified. sub address 0x22 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rev1 rev0 did5 did4 did3 did2 did1 did0 default value 0 0 1 1 0 1 0 1 device and revision id register definition bit register name r/w definition bit 0 ~ bit 5 did0 ~ did5 device id r device id indicator (0x35) bit 6 ~ bit 7 rev0 ~ rev1 revision id r revision id indicator (initially 0x00)
[AK8853XQ/ vn] rev-e-00 66 2008/01 11. system connection example 47 30 ain1 0.033uf 0.1uf 0.1uf vrp vcom vrn sda scl rstn pdn micro processor (i 2 c controller) oe data[7:0] nsig dtclk dvalid_f vd_f hd a nalog gnd digital gnd test0 a k8853 iref video in pvdd1 pvdd1 test1 ain2 clkmd 6.8k 0.1uf 10uf pvdd2 pull ? up 0.1uf xti 24.576mhz xto 22pf 22pf sela pvdd2 pvdd2 0.1uf 10uf dvdd dvdd 0.1uf 10uf dvss dvss ain3 ain4 a tio dvss avdd avdd 0.1uf 10uf avss
[AK8853XQ/ vn] rev-e-00 67 2008/01 12. package (AK8853XQ) 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.19 0.05 0.10 37 24 25 36 0~10 0.10 m 1.0 0.5 0.5 0.2 0.17 0.05 0.10 0.07 1.4typ 1.60max
[AK8853XQ/ vn] rev-e-00 68 2008/01 (ak8853vn) 7.200.10 7.000.05 7.200.10 7.000.05 c0.6 3-c0.2 0.220.05 0.05 m s a b a b 1 48 13 36 37 24 25 12 0.05 s 0.170.05 0.02 -0.015 +0.02 0.920.08 s 0.25 +0.40 -0.15 0.170.05 0.350.12 12 13 48 25 24 37 36 1 45 45 3-0.50 +0.40 -0.15 0.50
[AK8853XQ/ vn] rev-e-00 69 2008/01 13. marking (AK8853XQ) 1 a km AK8853XQ xxxxxxx akm: akm logo AK8853XQ: marketing code xxxxxxx (7 digits): date code (ak8853vn) 1 a km ak8853vn xxxxxxx akm: akm logo ak8853vn: marketing code xxxxxxx (7 digits): date code
[AK8853XQ/ vn] rev-e-00 70 2008/01 these products and their specifications are subject to change without notice. before considering any use or applicatio n, consult the asahi kase i microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative dire ctor of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether direct ly or indirectly, in the loss of the safety or effectiveness of the device or syst em containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the produc t with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hol d akm harmless from any and all claims arising from the use of said produc t in the absence of such notification. important notice

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